Episode 4 — From FinFET to Gate-All-Around Nanosheets

"Wrapping the Gate All the Way Around to Keep Moore's Law Breathing"

Pillar: Semiconductors & VLSI · Runtime ~13 min · ~2,000 words · Elena & Marcus

MARCUS: Episode four. We've stayed at the system level — grids, radios, motors. Today we go all the way down into the transistor itself, because the device under everything changed shape twice in the last fifteen years, and most working engineers never got the clean explanation of why. Elena, objective.

ELENA: By the end you'll understand the single problem that has driven transistor architecture for two decades — losing electrostatic control of the channel — and how the industry answered it by physically wrapping the gate further and further around that channel: planar, then FinFET, then gate-all-around nanosheets. We'll re-derive the short-channel effects that forced it, so the geometry feels inevitable rather than arbitrary.

MARCUS: The hook?

ELENA: Every transistor generation since about 2011 is the same story told with more sides. The gate started on top of the channel, then it grabbed three sides, and now it wraps all four. The reason is always the same: whoever controls the channel's electrostatics wins, and at these dimensions the only way to win is to surround it.

The Refresher: Dennard's Death and Short-Channel Effects

ELENA: Let's rebuild the physics, because the whole episode hangs on one idea: a MOSFET is a device where the gate is supposed to have total electrostatic authority over the channel, and the drain is not supposed to interfere. As long as that's true, the transistor switches crisply. The history of the last twenty years is the story of the drain stealing authority from the gate, and engineers fighting to take it back.

MARCUS: Start with why simple scaling stopped working.

ELENA: For decades we had Dennard scaling — the gift that powered Moore's law. The idea: shrink every dimension and the supply voltage together by the same factor, hold the electric field constant, and you get transistors that are smaller, faster, and lower-power all at once, generation after generation. It was close to a free lunch. And it died — really by the mid-2000s — for a specific reason. You couldn't keep scaling the voltage down, because the threshold voltage couldn't follow without leakage exploding. And once voltage stopped scaling while dimensions kept shrinking, the electric fields went up and power density started climbing instead of staying flat. That's the end of Dennard scaling, and it's why clock speeds stalled around then and we went multicore instead.

MARCUS: Now the short-channel effects — that's the leakage story.

ELENA: Right, let's make them concrete because they justify every architecture that follows. In a long-channel transistor, the gate sits over a channel that's long compared to its depth, and the gate fully controls whether the channel conducts. The drain is far away and minds its own business. Now shrink the channel length toward the same scale as the depletion regions around source and drain, and several bad things happen at once. The first is drain-induced barrier lowering, DIBL: the drain's own electric field reaches across the short channel and lowers the energy barrier the gate is trying to hold up. The drain starts turning the transistor on, partially, which is exactly what the gate is supposed to exclusively control. Threshold voltage sags as you raise the drain voltage. The second is threshold roll-off — short devices just have a lower, less controllable threshold. The net effect: leakage current when the transistor is supposed to be off climbs steeply.

MARCUS: And there's a hard floor on how sharply you can switch at all, right?

ELENA: Yes, and it's worth naming because it bounds everything. The subthreshold swing — how many millivolts of gate voltage you need to change the current by a factor of ten, below threshold — has a fundamental room-temperature floor of about sixty millivolts per decade for a conventional MOSFET. That's thermodynamics — the Boltzmann distribution of carriers — not an engineering limit you can polish away. So you have two pressures: a hard floor on switching steepness, and short-channel effects that push your actual swing well above even that floor as the gate loses grip. The entire job of advanced transistor architecture is to get the real device as close to that sixty-millivolt floor as possible by restoring the gate's control of the channel.

What Changed: The Gate Started Wrapping Around

ELENA: So here's the shift, and it's a beautifully physical one. If the problem is that the drain is reaching into the channel and the gate is losing its grip, the solution is geometric: get the gate closer to all of the channel so it dominates the electrostatics and the drain can't get a foothold. Put differently — increase the fraction of the channel that the gate physically surrounds.

MARCUS: And in 2013, where were we on that spectrum?

ELENA: In 2013 the leading edge had just made the first big jump. Planar transistors — gate on top, controlling the channel from one side only — hit a wall around the 22-nanometer node. The drain simply had too much influence from the sides and underneath, where the gate had no presence. Intel's answer, in production from 2011 to 2012 at 22 nanometers, was the FinFET — sometimes called Tri-Gate. You take the channel and stand it up on its edge into a thin vertical fin, and you drape the gate over it so the gate now touches the channel on three sides — both sidewalls and the top. Suddenly the gate has far more control, the short-channel effects are dramatically suppressed, the subthreshold swing gets close to ideal, leakage drops, and you can lower the voltage again. FinFET is what kept scaling alive from roughly the 22-nanometer node down through the single-digit nanometer nodes. That was the state of the art your 2013 self was watching arrive.

The Mechanism: Why More Sides Is Better, and Fin's Limit

ELENA: Let me make the "more sides" intuition rigorous, because it's the load-bearing idea. Think of the channel as territory and electrostatic field lines as influence. Every field line that terminates on the gate is the gate's control. Every field line that terminates on the drain instead is the drain leaking in — that's your DIBL, your leakage. In a planar device the gate only covers the top, so there are plenty of paths for the drain's influence to sneak through the sides and bottom. Wrap the gate onto three sides with a fin and you've cut off most of those paths — the gate intercepts far more of the field lines, the drain is boxed out. The figure of merit engineers use is keeping the gate length comfortably longer than a characteristic "natural length" that depends on how completely the gate surrounds the channel; more surrounding sides shrinks that natural length and lets you keep scaling the gate.

MARCUS: So if three sides is good, four sides is the obvious next move.

ELENA: It's the inevitable next move, and that's gate-all-around. But there's a specific limitation of the fin that also pushes you there, and it's worth understanding because it's a design limitation, not just a leakage one. In a FinFET, the channel width — which sets how much current, how much drive strength the transistor has — is the perimeter the gate wraps: twice the fin height plus the fin width. And both of those are fixed by the process. So you can only get more drive by adding more fins, in whole-fin increments. Drive strength is quantized. You want a transistor that's one-and-a-half fins strong? You can't have it — you get one fin or two. That quantization is a real constraint on how finely circuit designers can size devices.

Gate-All-Around Nanosheets

ELENA: So now the modern architecture, the one that defines the two-nanometer-class nodes rolling out right now. Gate-all-around. Instead of one tall vertical fin with the gate on three sides, you lay the channel down as a stack of thin horizontal sheets — nanosheets, sometimes called nanoribbons — and you grow the gate material completely around each sheet, all four sides. The gate now totally surrounds the channel. Maximum possible electrostatic control. The drain's reach is minimized about as far as geometry allows. Subthreshold swing as close to that sixty-millivolt floor as a silicon MOSFET gets, lowest leakage, ability to keep scaling the gate length down further.

MARCUS: And it fixes the quantization problem you just described?

ELENA: That's the elegant bonus. Because the channel is now a horizontal sheet, the transistor's drive strength is set by the width of that sheet — and you can draw the sheet wider or narrower at design time. Width becomes a continuous-ish design knob again instead of being quantized to whole fins. So gate-all-around buys you two things at once: better electrostatics from wrapping the fourth side, and finer control over drive strength from tunable sheet width. That's why Samsung — who calls their flavor MBCFET, multi-bridge channel — went to it at three nanometers around 2022, and why TSMC's N2 node and Intel's 18A, which Intel brands RibbonFET, are gate-all-around. The two-nanometer generation is a gate-all-around generation, full stop.

MARCUS: You mentioned earlier there's a power-delivery change riding along with this. What's that?

ELENA: Backside power delivery, and it's a genuinely big deal that arrived alongside gate-all-around. Traditionally both the signal wires and the power wires are stacked above the transistors, all fighting for the same routing space, and the power network has to snake down through many metal layers, picking up resistance and voltage droop. Backside power delivery flips the wafer and routes the power rails on the back of the silicon, directly underneath the transistors, while signals route on top. Power and signal stop competing, the power network gets fatter and lower-resistance, droop improves, and signal routing gets less congested. Intel calls their version PowerVia. So the modern node is really two changes bundled: gate-all-around transistors and backside power. And the next thing on the whiteboard beyond that is CFET — complementary FET — literally stacking the n-type transistor on top of the p-type to halve the footprint. The theme never stops: when you run out of room in the plane, you go into the third dimension.

Industry Standard Today

MARCUS: Pin down where the industry actually is.

ELENA: As of the mid-2020s: FinFET still does enormous volume across mature and not-quite-leading nodes — it's a workhorse and will be for years. The leading edge, the two-nanometer-class nodes entering high-volume manufacturing right now, is gate-all-around nanosheets — Samsung's three-nanometer MBCFET was first to production, with TSMC's N2 and Intel's 18A RibbonFET as the marquee two-nanometer-generation processes, the latter pairing gate-all-around with backside power delivery. And all of this is enabled underneath by EUV lithography — extreme-ultraviolet — which is its own catch-up topic worth a future episode, because patterning features this small is where a whole other set of physics, like stochastic edge roughness, takes over. But the headline for today: the transistor became three-dimensional to keep the gate in control, and gate-all-around is where that arc has arrived.

Self-Test

MARCUS: Turn it into skill.

ELENA: Two exercises. The first is quantitative and it anchors the whole episode in the floor we kept invoking. Take the subthreshold swing. With a swing near the ideal sixty millivolts per decade versus a degraded short-channel device at, say, ninety or a hundred millivolts per decade, work out how much the off-state leakage current differs for the same threshold voltage — remember each "decade" is a factor of ten in current. You'll find the degraded device leaks orders of magnitude more, and you'll feel why getting the swing back toward sixty — which is exactly what wrapping the gate buys you — is worth redesigning the entire transistor for. Leakage times billions of transistors is your chip's standby power.

MARCUS: And the second?

ELENA: The conceptual proof. Explain, in field-line terms, why gate-all-around suppresses drain-induced barrier lowering better than a FinFET, which beats planar — and then add the second advantage that has nothing to do with leakage: why nanosheet width gives designers finer drive-strength control than fin quantization does. If you can give both the electrostatic reason and the design-knob reason for moving to gate-all-around, you understand why the entire leading edge made the jump. That's the catch-up complete.

MARCUS: That closes Season 1's main arc — power, communications, control, and devices. Next episode is our fifth, and it loops back to energy with a skill that quietly runs every battery you own: estimating state of charge, and why the honest answer involves a Kalman filter.

ELENA: It's a satisfying place to end, because it fuses two of our pillars — power and estimation — into one practical algorithm. Bring the idea of "trust the model and the measurement in proportion to how much you trust each." That sentence is the whole next episode.