From FinFET to Gate-All-Around Nanosheets

"Wrapping the gate all the way around to keep Moore's law breathing."

⏱ ~13 minHosts: Elena & Marcus Read the transcript Companion notes (PDF)

In this episode

One idea drives twenty years of transistor architecture: the gate is supposed to have total electrostatic authority over the channel, and the drain is not supposed to interfere. We re-derive how that breaks down — the death of Dennard scaling, and the short-channel effects (DIBL, V_t roll-off, the ~60 mV/decade subthreshold-swing floor) that appear as the gate loses grip. Planar MOSFETs hit a wall around 22 nm; the FinFET answered by draping the gate over three sides of a vertical fin. The natural next move — and the defining feature of today's 2 nm-class nodes — is gate-all-around nanosheets, where the gate wraps all four sides for maximum electrostatic control and restores tunable drive strength (sheet width) that the fin had quantized. Riding alongside: backside power delivery, with CFET stacking on the horizon.

Lesson map

ObjectiveUnderstand the one problem — losing channel control — that drove planar → FinFET → GAA.
The refresherDennard scaling's death; DIBL, V_t roll-off, and the ~60 mV/dec subthreshold floor.
What changedGet the gate closer to all of the channel; planar wall ~22 nm; FinFET's three-sided grip.
The mechanismField-line intuition for "more sides = more control," and the fin's width-quantization limit.
Gate-all-aroundFour-sided nanosheets, tunable width, MBCFET / RibbonFET, plus backside power delivery and CFET.
Industry standard + self-testWhere FinFET vs. GAA sit today, EUV flagged, two exercises.

Key concepts

Dennard scalingDIBLSubthreshold swing (≈60 mV/dec)V_t roll-off Off-state leakageFinFET / Tri-GateElectrostatic controlWidth quantization Gate-all-around / nanosheetMBCFET / RibbonFETBackside power delivery CFETEUV (flagged)

Self-test

1 · Leakage and the subthreshold swing

Compare off-state leakage for a device near the ideal ~60 mV/decade swing versus a degraded short-channel device at ~90–100 mV/decade, for the same threshold voltage. Remember each "decade" is a factor of ten in current — you'll find orders-of-magnitude more leakage, times billions of transistors. That's why getting the swing back toward 60 mV/dec is worth redesigning the whole transistor.

2 · Why GAA beats FinFET beats planar

In field-line terms, explain why gate-all-around suppresses DIBL better than a FinFET, which beats planar. Then add the second, non-leakage advantage: why nanosheet width gives finer drive-strength control than fin quantization. Give both reasons and you understand why the leading edge made the jump.

Warm up in CircuitQuEEst

The matching undergraduate foundations are quests in CircuitQuEEst, the free, offline Android app for learning EE (download the APK). Play these first, then come back for the graduate-level version:

Semiconductor Physics — Carrier Transport: the diffusion current behind subthreshold leakage.
MOSFETs — Operating Regions: the app treats cutoff as fully off; this episode is about the current that still flows.
VLSI Design — CMOS Fabrication Process · Power Optimization: why leakage times billions of transistors matters.

Go deeper

Intel 22 nm Tri-Gate (2011–12) — the first high-volume FinFET.
Samsung 3 nm MBCFET (2022) — first gate-all-around in production.
TSMC N2 & Intel 18A (RibbonFET + PowerVia) — the 2 nm-class GAA generation with backside power.
CFET roadmap & EUV lithography — stacking n-over-p, and the patterning physics (a future episode).

Node names and years follow vendor announcements; see vendor disclosures for specifics.